The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a technique which may effectively be used for a semiconductor integrated circuit device having a static random-access memory (hereinafter referred to as "SRAM").
Each of the memory cells of a typical conventional SRAM is, for example, composed of a flip-flop circuit comprising two high resistance load elements and two driving MISFETs (Metal Insulator Semiconductor Field Effect Transistors), and two transfer MISFETs which are respectively connected to a pair of input/output terminals of the flip-flop circuit. The high-resistance load elements are constituted by a polycrystalline silicon film which is formed integrally with a power source voltage wiring for the purpose of reducing the memory cell area and thereby achieving a larger integration. Such SRAM is disclosed in, for example, U.S. Pat. No. 4,554,729 (Japanese Patent Laid-Open No. 130461/1982) registered on Nov. 26, 1985.